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resistion
All indications are Intel will use multiple patterning without EUV for 10 nm. ...
resistion
http://www.theregister.co.uk/2013/05/29/euv_lithography_still_out_there/
GloFo, Samsung in race to 14 nm
Rick Merritt
2/6/2013 5:00 AM EST
Race to 14-nm FinFETs
Meanwhile a race to next-gen node continues. To accelerate progress the Common Platform partners agreed that starting this year technology developed at the group’s Albany, New York, facility will be directly transferred to partners. Previously it went first to IBM’s Yorktown, New York fab, then to partners.
“We just eliminated a step to market,” said IBM’s Patton.
Globalfoundries and Samsung are both running test shuttles this year for 14 nm with FinFETs. Both aim to have their first production wafers out by the end of the year if all goes well.
Globalfoundries reported more than 60 percent improvements in power or performance at 14 nm compared to 28 nm, based on a test chip using a dual-core ARM Cortex A9. In addition, it is working with Synopsys on an EDA flow and with Rambus on migrating 28 nm IP to the new node.
Click on image to enlarge.
K.H. Kim, executive vice president of Samsung's foundry business, said the company will run 14 nm test shuttles for select customers in April and September. It has 14 nm IP partnerships with ARM, Synopsys and Analog Bits.
Meanwhile, Samsung is converting its Austin, Texas fab from memory to logic, expecting the first 28 nm wafers from it this year. It also will produce 20 and 14 nm wafers starting as early as the end of 2014 in a new fab in Korea.
“We will have enough capacity to serve you,” Kim told attendees in a keynote.
Click on image to enlarge.
It’s not clear how much chip designers will demand the 14 nm FinFET process which carries significant costs and marginal advantages over a coming 20 nm node.
The 20 nm node is the first to require double patterning, a cost adder. The 14 nm node is essentially a 20 nm process with FinFETs, another cost, said IBM’s Patton.
“It’s not a true shrink, but when you get to 10 nm it is a true shrink and I expect significant cost benefits,” Patton said. “Is there still a cost benefit [with 14 nm]? Absolutely, it just won’t be as large as it was historically,” he added.
“We believe 28 nm will be a very long node, a very cost competitive solution,” said Kim.
Market watcher Handel Jones of International Business Strategies (Los Gatos, Calif.) said FinFETs present real challenges for mixed-signal designs, potentially delaying the node’s ramp.
Nevertheless, he said Globalfoundries and Samsung have a significant opportunity to grab market share from TSMC. In addition, IBM’s Burlington fab is doing “extremely well” in RF, he added.
Meanwhile a race to next-gen node continues. To accelerate progress the Common Platform partners agreed that starting this year technology developed at the group’s Albany, New York, facility will be directly transferred to partners. Previously it went first to IBM’s Yorktown, New York fab, then to partners.
“We just eliminated a step to market,” said IBM’s Patton.
Globalfoundries and Samsung are both running test shuttles this year for 14 nm with FinFETs. Both aim to have their first production wafers out by the end of the year if all goes well.
Globalfoundries reported more than 60 percent improvements in power or performance at 14 nm compared to 28 nm, based on a test chip using a dual-core ARM Cortex A9. In addition, it is working with Synopsys on an EDA flow and with Rambus on migrating 28 nm IP to the new node.
Click on image to enlarge.
Globalfoundries says a dual-core A9 test chip showed 14 nm gives 60%+ boost over 28 nm.
K.H. Kim, executive vice president of Samsung's foundry business, said the company will run 14 nm test shuttles for select customers in April and September. It has 14 nm IP partnerships with ARM, Synopsys and Analog Bits.
Meanwhile, Samsung is converting its Austin, Texas fab from memory to logic, expecting the first 28 nm wafers from it this year. It also will produce 20 and 14 nm wafers starting as early as the end of 2014 in a new fab in Korea.
“We will have enough capacity to serve you,” Kim told attendees in a keynote.
Click on image to enlarge.
Samsung readies two 14 nm shuttles this year with hopes for production wafers before January.
It’s not clear how much chip designers will demand the 14 nm FinFET process which carries significant costs and marginal advantages over a coming 20 nm node.
The 20 nm node is the first to require double patterning, a cost adder. The 14 nm node is essentially a 20 nm process with FinFETs, another cost, said IBM’s Patton.
“It’s not a true shrink, but when you get to 10 nm it is a true shrink and I expect significant cost benefits,” Patton said. “Is there still a cost benefit [with 14 nm]? Absolutely, it just won’t be as large as it was historically,” he added.
“We believe 28 nm will be a very long node, a very cost competitive solution,” said Kim.
Market watcher Handel Jones of International Business Strategies (Los Gatos, Calif.) said FinFETs present real challenges for mixed-signal designs, potentially delaying the node’s ramp.
Nevertheless, he said Globalfoundries and Samsung have a significant opportunity to grab market share from TSMC. In addition, IBM’s Burlington fab is doing “extremely well” in RF, he added.
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yalanand
2/6/2013 6:33 AM EST
So industry is already thinking about 7nm ? How far we can shrink the transistor ? I think we are approaching the limit and soon companies will start building new architecture's to enhance the performance instead of worry about shrinking the transistor.
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resistion
2/6/2013 9:09 AM EST
"The companies said they now expect EUV will not be ready until the 7-nm node." NXE can't do 7 nm either.
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rick.merritt
2/6/2013 11:03 AM EST
Why not?
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resistion
2/6/2013 12:28 PM EST
The NXE resolution spec is 22 nm, 16 nm at best. Not 7 nm.
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the_floating_ gate
2/6/2013 1:21 PM EST
This would explain why TSMC sticks with 16nm rather 14nm.
I believe back in July during ASML CC ASML stated that foundries face additional challenge compared to IDM due to design rules / (aggressive) shrinkfactor and the conclusion from what I recall was that foundries would need EUV @14nm.
I believe they also stated that DRAM people would be first in adopting EUV.
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resistion
2/11/2013 8:47 PM EST
DRAM companies already moving on to 2x nm, so they're not waiting for EUV either.
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rick.merritt
2/6/2013 1:52 PM EST
I am assuming NXE is the ASML immersion litho system.
At 20 nm Patton said folks need to start doing double patterning. Beyond that they are pulling out all the stops to minimize the need for triple and quad patterning.
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any1
2/6/2013 2:36 PM EST
NXE is EUV, NXT is 193 nm immmersion. I think it's a little early to spend much time thinking about 7 nm node today. But if we only have the currently expected EUV technology, we would have to use double patterning.
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minimal.ath
2/6/2013 2:37 PM EST
Hi Rick. NXE's are EUV machines. Immersion systems are the NXT's and those with an 'i' after a number.
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Plasmon
2/9/2013 7:39 AM EST
"7nm" is the name of the node, not the CD needed to print. See ITRS roadmap or Wikipedia for details. Thanks
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resistion
2/9/2013 9:21 AM EST
It can't be gate length anymore but it might be fin CD.
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iniewski
2/6/2013 10:38 AM EST
7nm??? that is beyond 10nm that everyone thought is the end of scaling...how many dopants are left in MOSFET at this scale? five? ;-)
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OtisTD
2/6/2013 11:35 AM EST
Fully depleted technologies like FDSOI and FinFET use undoped channels- so basically zero dopants, except for the source and drain. Of course there may be some doping of Fins for various reasons in the early implementations, but ultimately it will be undoped channels. And junctionless transistors have been demonstrated as well if you are worried about the S/D doping.
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OtisTD
2/6/2013 11:39 AM EST
Oh and P.S. "everyone thought" 100nm was the limit at one time as well. I have yet to hear Intel, IBM, Samsung, TSMC or any IDM/Foundry say there is any hard limit in the foreseeable future. The limit will come from economics, not physics- it will just get too expensive to stay on Moore's law at some point.
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rick.merritt
2/6/2013 10:01 PM EST
So even EUV would require double patterning at 7 nm?
Oi vay!
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resistion
2/6/2013 11:46 PM EST
Maybe even triple, 16 over 7 ~2.3.
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the_floating_ gate
2/6/2013 11:24 AM EST
I am wondering if Samsung/Gloflo "roadmap" was backed up by a manufacturing/litho roadmap.
I clicked on the slides - one said 14nm on track...
I would imagine being a customer you would want to now what process you actually use before taping it out?
ASML mentioned that foundry process would require EUV @14nm - I am curious why TSMC selected 16nm FinFet as next generation following 20nm planar.
"It’s not clear how much chip designers will demand the 14 nm FinFET process which carries significant costs and marginal advantages over a coming 20 nm node."
Shouldn't they figure this out?
I get impression they just follow blindly Intel roadmap.
The 20 nm node is the first to require double patterning, a cost adder. The 14 nm node is essentially a 20 nm process with FinFETs, another cost, said IBM’s Patton.
That comes from an "IBMer" - makes me scratch my head -
imagine you are a potential customer and you evaluate TSMC, Gloflo and Samsung.
which one would you pick?
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OtisTD
2/6/2013 11:47 AM EST
Surprised the article didn't mention DSA prominently (directed self assembly)- they spent some time on that as well and that can reduce the need for double/triple/quadruple patterning as well. That is one area where IBM has made some real advances. But I don't recall seeing any litho roadmap slide- no.
And to their credit (contrary to your impression) they don't seem to be following blindly the Intel roadmap. K. Kuhn and M. Bohr have been touting tunnel FETs and Ge/III-V channels lately. IBM basically dismissed those solutions and said Si nanowire followed by carbon nanotubes is how they think it will go.
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rick.merritt
2/6/2013 1:54 PM EST
I plan a separate slideshow using several foils on DSA and other double patterning tricks Patton talked about. Stay tuned.
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Red Hog
2/6/2013 3:14 PM EST
Rick what does first production silicon by end of the year mean?
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rick.merritt
2/6/2013 10:03 PM EST
Good question.
GloFo calls it "risk" production.
Samsung just calls it "production."
I would assume it is a step short of volume production but clearly out of the test shuttle stage.
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SiliconAsia
2/7/2013 11:56 AM EST
Fabless-foundry model is broken and TSMC is recently quoting the mask NRE of 16/14nm finfet over $10M. Even this goes down to below $10M over time, the NRE for 10nm or 7nm will be prohibitable for many except a few like Qualcomm, Apple, Samsung and maybe Nvidia, Broadcom and Marvell. The rest will be consolidated and disappear. Only analog/power semi guys will stay and digital is pretty much owned by a few.
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the_floating_ gate
2/7/2013 1:27 PM EST
Samsung will rule ARM world:
1.) they have their own fabs
they are foundry and IDM;
and they compete directly with their customers (Apple)
2.)they leverage NAND, LPDRAM and display cutting out the middleman
Apple gave Samsung business and they created a monster.
It's going to be a repeat when Samsung entered the DRAM market about 25 (?) years ago.
"Only analog/power semi guys will stay and digital is pretty much owned by a few."
IMHO that's exactly why TI quit mobile business
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joshxdr
2/7/2013 10:04 PM EST
Does that imply that Samsung will rule the foundry world? Will they take over from Intel the mantle of logic process technology leader?
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resistion
2/7/2013 10:11 PM EST
Indeed,the benefit of vertical integration from silicon design to product.
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mranderson
2/7/2013 10:13 PM EST
I would say that there are several more customers. People are willing to pay for advances in consumer and industrial electronics, but more products will become commodities with only software and firmware to provide differentiation. Many cell phone designs are already starting to look and feel similar to each other. I would not be surprised though to see people sneak in a special 28nm chip for example into their designs for some hardware customization for say a 8 inch or larger tablet form factor device.
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Diogenes53
2/7/2013 10:46 PM EST
Some of us have been saying for years that the pursuit of x-ray lithography, whether hard x-ray (~1nm) or soft x-ray (~13nm), a.k.a. EUV, was a supreme waste of millions of man-hours and billions of dollars. There were source/mask/resist issues 25 years ago, and there are source/mask/resist issues today. The pursuit of shiny penny alternatives continued, each of them with source, mask, and/or resist issues. The latest distraction is direct self-assembly. Good luck with that. Meanwhile, the choice was clear: shut down Moore's Law and its replenishable pot of gold, or extend optical. If optical was to be extended beyond what most folks thought possible, it would be essential to integrate design and manufacturing, which would result is the re-integration of the disaggregated semiconductor industry, and consequently, the ultimate supremacy of the old-fashioned IDM. Wonder if EUV/x-ray will be ready at 500 angstroms? Let's see: how large will the OPC features be. Or is that XPC?
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michigan
2/8/2013 2:40 AM EST
Scalability of the planer bulk technology ends at 28nm because world major foundries; TSMC, Samsung, GlobalFoundries, and UMC all get on to Intel’s FinFET bandwagon after falling behind Intel. They all plan to introduce FDFinFETs at 14nm node in 2014, skipping the 22nm, at the same time of Intel’s 14nm introduction. The foundries schedule looks unrealistic, and planed aggressively not to behind falling too far behind Intel. It leaves IBM being the only major company adopting FDSOI scaled to 10nm. For 22nm FDSOI about 6nm SOI thickness is required to suppress transistor leakage current, while for 22nm FDFinFET the fin width as large as 22nm is required to suppress the transistor leakage current. In my opinion that is the main reason why Intel’s 22nm FinFETs are in high volume manufacturing today for more than a year, but 22nm FDSOI is not. For 14nm FDSOI about 4nm SOI is required while for 14nm FinFETs the fin width as large as 14nm is required to suppress transistor leakage currents. Thus, FDFinFETs show large advantages in manufacturability as transistor is scaled. Soitec can deliver today only the 28nm SOI wafers with 12nm SOI and 25nm buried oxide. Skim
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help.fulguy
2/11/2013 6:33 PM EST
Bunch of losers. Ages behind Intel.
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resistion
6/12/2013 11:57 AM EDT
http://www.theregister.co.uk/2013/05/29/euv_lithography_still_out_there/
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resistion
6/12/2013 7:52 PM EDT
All indications are Intel will use multiple patterning without EUV for 10 nm. The other foundries will likely follow.
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nannasin28
3/19/2013 3:17 AM EDT
it would be essential to integrate design and manufacturing. http://www.hqew.net
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nannasin28
4/7/2013 4:32 AM EDT
These are real physics problems we have to solve.http://www.hqew.net
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