Analysts start Intel Ivy Bridge CPU teardown

SAN JOSE – UBM TechInsights started a teardown analysis of an Intel Ivy Bridge processor. The Ivy Bridge chips are the first to use Intel’s 22 nm process technology with 3-D transistors and have yet to be officially launched.

Some Web reports speculate Intel may formally launch Ivy Bridge chips as early as April 29. Other reports have said the launch could be delayed until July.

An Intel spokesman said the official launch of the chip will be “very soon.” He added that “we have been in production of the chip since late last year,” likely meaning in sample quantities for most of that time.

UBM TechInsights has an Ivy Bridge processor marked as a 3.3GHz Core i5-3550 chip packaged in Malaysia. It has a die size of 170 mm², down from 208 mm² for the current Sandy Bridge i7 2600K CPU.

In its initial tests, UBM TechInsights found gate pitches of 90nm in the embedded SRAM array in the processor. It also found logic regions with gate lengths of 22 nm.

The exact naming of a process generation is part art and science, expert say. Even inside Intel debates rage about exactly what gate lengths to use as a name for a chip process.

Most of the semiconductor industry has said the next big process is a 28 nm technology. Altera and Xilinx have already shipped 28 nm FPGAs, and AMD and Qualcomm have 28 nm processors in progress now.

Intel's 22 nm technology is unique in its use of 3-D transistors otherwise known as FinFETs. The transistor designs are supposed to lower power leakage, one of the biggest problems for current state-of-the-art chips. Other chip makers say they will deploy similar technologies in sub 20 nm processes.

UBM TechInsights aims to deliver two reports based on its examination of the Ivy Bridge chip. It will release about May 4 a logic detail structural analysis report covering the chip’s process technology, embedded memory, logic cells, logic and I/O transistors with high res images of the chip and its key regions.

The company aims to deliver about May 18 a second report on transistor characteristics of the CPU. It will include an analysis of the DC electrical properties of the chip’s NMOS and PMOS transistors, data on its gate and channel leakage current and performance benchmarks measured at three temperature levels.

The analysis will include use of Scanning and Transmission Electron Microscopy, Spreading Resistance Profiling and X-ray techniques. UBM TechInsights is a sister division of UBM LLC, the publisher of EE Times.