ISSCC: Intel focuses on low power, digital RF

SAN JOSE, Calif. – Intel will show progress in research efforts to deliver more power efficient processors and digital RF capabilities at the International Solid State Circuits Conference. It will also give one of the first in-depth public disclosures of a next-generation Ivy Bridge processor.

ISSCC will play host to more than 200 papers on novel developments in chip design from around the world. The papers span the gamut from advances in memory technology, medical electronics and more. In addition, top research groups including Europe’s Imec and nanotech researchers will talk about their latest work.

For its part, the world’s largest semiconductor company will present more than a dozen papers, many of them detailing research work using its new 22 nm tri-gate process technology. Creating more power efficient products is a focus for many of the ISSCC papers from Intel and from ISSCC as a whole.

In a handful of mainly research papers, Intel will describe techniques to deliver five- to ten-fold power efficiency gains by driving circuits to perform at near threshold voltage levels.

“Energy efficiency peaks as you approach threshold voltage,” said Justin Rattner, chief technology officer for Intel in an ISSCC briefing. “Taking systems to very low voltage but not putting them in standby allows meaningful operation,” he said.

Intel demoed at its own IDF Fall event last year its Claremont processor, a research chip running at such low voltages it could actually be powered up by a tiny handheld solar cell. Intel doesn’t aim to build solar-powered CPUs, quipped Rattner, but it does aim to explore how low it can go in getting work out of chips at the lowest power levels.

At ISSCC, Intel will give an in-depth discussion of the Claremont chip (paper 3.6). It will also describe an effort (paper 13.3) using similar techniques for a bank of 22 nm eight-transistor SRAMs used as a CPU cache

Another paper (10.1) will detail a 256-bit wide SIMD graphics block made in a 22 nm process operating at 280 millivolts for a nine-fold efficiency gain. “Due to using a ground up design we got close to order of magnitude improve in energy efficiency, something that’s almost unheard of,” Rattner said.

A related paper (10.3) will discuss a floating point unit that saves 50 percent energy by reducing precision from 24- down to six significant digits without loss of accuracy.

Separately, Intel will present a handful of papers on advances in digital processing in RF, focused mainly on work in 2.4 GHz Wi-Fi.

“We are getting close to having a complete kit of digital RF building blocks for radios,” said Rattner. “The next step in research is to integrate these blocks on SoCs with digital logic circuits,” he said.

In one paper (3.4) Intel will describe Rosepoint, a research chip that embeds a full 2.4 GHz Wi-Fi transceiver using digital RF techniques in a dual-core 32 nm Atom processor. Commercial versions of such chips could emerge by mid-decade, Rattner said, likely first appearing as standalone digital RF transceivers.

The Atom prototype includes a digital 2.4 GHz RF transmitter Intel will describe in a separate paper (9.4). “It’s not just the power amp which is part of this design, but also a digital phase modulator for Wi-Fi that uses two digital signals in phase to provide OFDM modulation,” he said.

“We can now build a Wi-Fi radio and hopefully in the not too distant future a cellular radio to make digital RF practical for SoCs,” he added.

“You may have seen baseband MACs integrated [in mobile applications processors] but RF integration is very rare to non-existent [in commercial chips] and full digital integration has yet to come to any of these products--many of these blocks are the first of their ilk,” Rattner said.

Intel’s research group already has “transferred individual circuit blocks such as low noise power amps, ADCs, switching power amps and other blocks” to its product teams.

“I think we have covered the big blocks, but there is certainly work to do in interfaces,” Rattner said. “The challenge is to do enough risk reduction,” he said.

“Almost all these designs have second- or third-generation versions now in the labs,” he said.