EDA/IP weekly roundup – February 6th 2013

2/6/2013 11:00 AM EST

This is a roundup of news or activities in the past few days that may be of interest to people.

Cadence reported fourth quarter 2012 revenue of $346 million, compared to revenue of $308 million reported for the same period in 2011. On a GAAP basis, Cadence recognized net income of $314 million, or $1.10 per share on a diluted basis, in the fourth quarter of 2012, compared to net income of $11 million, or $0.04 per share on a diluted basis, in the same period in 2011. Revenue for 2012 totaled $1.326 billion, compared to revenue of $1.150 billion for 2011. Net income for 2012 was $440 million, or $1.57 per share on a diluted basis, compared to net income of $72 million, or $0.27 per share on a diluted basis, for 2011.

According to Semico, advanced technologies and the latest consumer electronics grab the major headlines but the semiconductor industry depends on mature technologies and legacy equipment. Today, about 40% of all silicon used to produce semiconductors are processed using mature manufacturing technologies. Manufacturing processes at 0.18 micron and larger still utilize 200mm and smaller wafer fabs. At the First Annual Collaborative Forum at the SEMI headquarters in San Jose, CA on Feb 6-7th, 2013, Joanne Itow, Semico's Managing Director, will be presenting on fab capacity and volume devices that continue to utilize mature technologies.

Cadence has production-proven verification IP (VIP) for the new USB SuperSpeed Inter-Chip (SSIC) specification. The SSIC specification combines the MIPI Alliance physical interface (M-PHY) with the upper layers of the USB protocol to enable USB 3.0 to connect chips within a mobile device. This makes it easier for mobile device manufacturers to leverage the large USB hardware and software ecosystem in the mobile environment.

DCD has a new IP block – DLIN a local interconnect network IP core which is fully compatible with LIN 1.3, 2.1 and the newest version 2.2 Revision A, released by the LIN Consortium. DLIN is a serial interconnect primarily utilized within the automotive industry to integrate intelligent sensor devices or actuators. Compared to CAN, LIN is slower, but thanks to its simplicity, it is much more cost effective. The core is described at RTL level.

Cadence has announced that GlobalFoundries has certified Cadence technologies for custom/analog, digital and mixed-signal design, implementation, and verification for its 20-nanometer LPM technology. The certification covers the Virtuoso and Encounter platforms, including the industry-standard SKILL process design kit (PDK).

GlobalFoundries announced results from the industry’s first implementation of a dual-core ARM® Cortex™-A9 processor using three-dimensional 14nm-XM FinFET transistors. Based on the industry standard design implementation flows and sign-off simulations using real process data, GlobalFoundries expects that a dual-core ARM Cortex-A9 processor manufactured on GlobalFoundries’ 14nm-XM technology will deliver more than twice the energy efficiency of a similar 28nm-SLP technology based design, while requiring only half the chip area.

GlobalFoundries and Synopsys have partnered to deliver a design solution to accelerate the implementation of GlobalFoundries’ 14 nm-XM FinFET offering. The solution includes Synopsys’ DesignWare® Embedded Memory and Logic Library IP; design tools from the Galaxy™ Implementation Platform; and TCAD process and device simulation tools, all optimized to enable design teams to achieve desired performance, power and area requirements in the most efficient, low-risk manner. The collaborative development is built on the industry’s first modular FinFET technology, which combines a 14 nanometer (nm) FinFET device with elements of GlobalFoundries’ 20 nm-LPM process to reduce risk and accelerate time to volume.

GlobalFoundries announced a partnership with Adapteva to offer the company’s Epiphany IV microarchitecture to customers using GlobalFoundries’ leading-edge 28nm-SLP process technology. The agreement will allow chip designers to integrate Adapteva’s massively parallel multicore technology into their next-generation system-on-chip (SoC) designs, enabling server-level performance in mobile devices such as smartphones and tablets.

Spending on research and development by semiconductor companies grew 7% in 2012 to a record-high $53.0 billion, even though the semiconductor market declined 1% to $317.6 billion, according to the 2013 edition of IC Insights’ McClean Report.  The increase lifted R&D spending by chip companies to 16.7% of total semiconductor sales in 2012, the highest level since the peak of 17.5% was reached in both 2008 and 2009.