SIGNAL CHAIN BASICS #60: Tracking down spurious signals in high-speed ADCs

(Editor's note: Signal Chain Basics is an ongoing and popular series; click here for a complete, linked list of all installments.)

     As their sample rates, resolutions and bandwidths increase, high-speed data converters are increasingly enabling new signal-chain architectures. Data converters, which span the digital and analog domains, are more complex to debug than an analog-=only signal chain. This article discusses approaches for tracking down spurious signals in high-speed analog-to-digital converter (ADC) systems.

     Figure 1 shows a typical high-speed ADC signal chain. There are several potential sources of spurious signals in the system:

1)     signal chain before ADC input

2)     the ADC itself

3)     sample clock

4)     power supplies

 

Figure 1: High-speed ADC signal chain.

    The first step in debugging the data converter is to measure the performance so that it can be compared to the expected performance. High-speed ADCs usually are characterized with a continuous wave (CW) input. While this may not reflect the actual system requirements, it is easier to track down spurious signals and compare to expected performance.

     To analyze the ADC output, you need to capture the digital output signal and examine the frequency domain by performing a fast fourier transform (FFT). If the input frequency is not coherent (an exact integer number of cycles in the length of the captured data), then a window function should be applied to the output data before FFT.

     The input signal should be filtered before being input to the system, as signal generators typically have very poor distortion leading to large harmonics. The peak-to-peak amplitude at the ADC can be measured in the ADC output data, and the input adjusted to the desired input level.

     There are several different types of spurious signals that can be generated in a system with ADCs. Due to the sampling nature of the ADC, spurs generated at frequencies above the 1^st Nyquist zone (0 – f_SAMPLE/2) will alias back into the Nyquist zone at the ADC output.

     While the frequency of the spurs at the output can be easily calculated, another method is to observe the change in output frequency with input frequency. There are also several types of spur behaviors.

1)     Harmonics generated by non-linear distortion, change in output frequency by:

 ±f_OUT = N × ±f_IN where ±f_IN is the change in input frequency, N is the order of the harmonic, and ±f_OUT is the change in frequency at the ADC output. For example, if the input frequency is shifted by 100 kHz and the observed output frequency moves by 500 kHz, then the spur is the 5^th harmonic.

Whether the harmonic comes from the ADC itself or is present on the input signal is more difficult to identify. For low order harmonics like the 2^nd or 3^rd harmonic, analog components ahead of the ADC input can generate these harmonics. One method to identify the source is to change the conditions in the signal chain ahead of the ADC and see if the harmonic amplitude changes (raising or lowering the amplifier supply slightly).

In a heterodyne radio system, the RF input and LO frequencies can be moved oppositely (for example f_IN = +1 MHz, F_LO = –1 MHz) so that the resulting IF output is constant. If the spur in the ADC spectrum moves, then the spur is likely related to the mixer or LO.

2)     The ADC sampling process acts like a mixer, so any spurs on the clock input will result in a spur at the ADC output. The frequency of clock spurs move 1:1 with the input frequency.

3)     Spurious signals that do not move with the input signal typically are generated by some source outside the signal chain and couple into the signal path.

4)     Switching regulators can generate spurs by coupling either through the input path, clock path, or the ADC power supplies. The characteristic of spurs due to switching regulator is that they are at a frequency or offset frequency of several hundred kHz. Switching regulators can be used successfully to power ADCs, but particular care in the interface to the ADC is require^d (Reference 1).

     Although this is not a complete list of all potential problems, most spurs will fall into one of these categories. The key to solving the problems in the data and methodology is to track down the source of the spur.

    Please join us next month when we talk about the relationship between jitter and phase noise in clocking applications.

References

1. Download your copy of this application report, titled: “Power Supply Design for the ADS41xx.”
2. Download a datasheet for the ADS4249 here: www.ti.com/ads4249-ca.
3. For more information on ADCs from TI, visit: www.ti.com/adc-ca.

About the Author

Robert Keller is the Systems and Applications Manager for High-Speed Data Converters. He has nine years experience supporting high-speed products in wireless infrastructure communication, test and measurement, and military systems. He received a B.A. in Physics and Mathematics from Washington University, St. Louis, and a Ph.D. in Applied Physics from Stanford University. He has 10 US patents in networking and sensor applications. Robert can be reached at ti_scb@list.ti.com. 

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