Who needs a hybrid?
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Penetration of Verification IP
Brian Bailey
How does the market for verification IP compare to design IP...
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DRC debugging challenges in AMS/custom designs at 20 nm
Srinivas Velivala, Mentor Graphics
The traditional DRC verification flow used by custom layout designers simply can’t provide the needed level of productivity when debugging DRC results at advanced nodes….
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Semi market contracted in 2012
Brian Bailey
According to IDC, the semiconductor market contracted 2.2% last year although larger companies saw bigger losses...
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EDA/IP weekly roundup – May 22nd 2013
Brian Bailey
Aldec, Avery, Berkeley, Cadence, Cypress, DAC, GlobalFoundries, IDC, Imec, Imperas, Mentor, Oasys, OpSIS, Real Intent, Renesas, Samsung, SEMI, Si2, Tezzaron and TSMC made the lineup today. See here for their news…
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The OpenDFM standard has achieved production support status for process nodes down to 28nm, and development support through 20nm…
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Preparing for DAC: Technical panels
Brian Bailey
There are eight panels at DAC this year. Which ones should you attend?
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